Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Reliability can be an important consideration in the design of microprocessors. In today's microprocessors, about 60% of the on-chip area may be occupied by caches. Because of that, caches may have a considerable impact on microprocessor reliability, area, and energy consumption. Caches often use a write-back policy where dirty data may not be immediately propagated to lower levels of the memory hierarchy. Since dirty data may have no back-up copies in other levels of the memory hierarchy, write-back caches can be more vulnerable to soft errors. To enhance reliability in write-back caches, two protection codes may be used:
1—SECDED (Single Error Correction Double Error Detection) ECC: This code is used in commercial processors. See J. Doweck, “Inside Intel Core™ Microarchitecture,” IEEE Symposium on High-Performance Chips, 2006; and McNairy, C. and Soltis, D., Itanium 2 processor micro architecture, IEEE Micro, vol. 23, Issue 2, pp. 44-55, 2003. However, the area overhead of SECDED can be high, as it takes 8 bits to protect a 64-bit word, a 12.5% area overhead. Furthermore, the energy overhead of SECDED can also be high.
2—Parity: Because the overheads of SECDED code may be high, some L1 caches are protected with parity bits. Parity bits can be effective in L1 write-through caches because they detect faults recoverable from the L2 cache, but they may not provide any correction capability for the dirty data of L1 write-back caches. In some processors, the L1 write-back cache may be protected by one parity bit per word such as in Power-QUICC™ III Processor; an exception may be taken whenever a fault is detected in a dirty block and program execution is halted. Hence, even a single-bit error in a write-back parity-protected cache may cause the processor to fail.